The present invention relates to an improvement providing integral avalanche protection for AC power FET structure such as shown in copending application Ser. Nos. 390,719 now abandoned and 390,479, filed June 21, 1982. These applications disclose lateral FET structure for bidirectional power switching, including AC application. Laterally spaced source regions and channel regions have a common drift region therebetween. Upon application of voltage of either polarity across main terminals connected to the source regions, current flow in either direction is controlled by the potential on gate electrode means proximate the channels.
The latter application shows notch gate structure wherein a notch extends downwardly from a top major surface to separate right and left source regions and right and left channel regions, and direct the drift region current path between the channels around the bottom of the notch. Gate electrode means is provided in the notch proximate the channels for controlling bidirectional conduction. In the OFF state of the FET, a reverse biased junction between the drift region and one FET channel blocks current flow toward one main terminal, and another reverse biased junction between the drift region and the other FET channel blocks current flow in the other direction towards the other main electrode.
A need has arisen in some implementations for protecting the reverse blocking junctions in the OFF state of the FET from transients or other overvoltage conditions causing avalanche breakdown. The present invention addresses and solves this need by providing integral avalanche protection for each of the junctions in the OFF state. Respective integral barrier junctions are provided in parallel with the respective blocking junctions in the OFF state and have a lower reverse breakover threshold, to conduct current in a bypass path around the blocking junctions to thus protect the latter.
In the preferred embodiment, a bottom layer is disposed beneath the drift region and is of opposite conductivity type. A pair of isolation regions of the same conductivity type as the drift region and the source regions are isolated from the source regions, channel regions and drift region by respective isolation moats extending down from a top major surface into the bottom layer. A first main electrode contacts the first source region and first channel region, and a second main electrode contacts the second source region and second channel region. Each main electrode also contacts a respective isolation region. The alternate bypass path between the main terminals is from one isolation region through the common bottom layer to the other isolation region, which path is in parallel with the FET path between the main terminals.